1. Field of the Invention
The present invention relates to a phase comparison circuit or, more particularly, to a circuit for detecting erroneous phase lock occurring when the duty cycle of data deviates from 100% during comparison of the data with a clock during which a phase difference between the data and clock is detected.
2. Description of the Related Art
At a receiving terminal station of an optical transmission system, synchronous reproduction is performed in order to convert a data wave, which is distorted due to the characteristic of an optical transmission line or convolution of noise, into an original fine digital signal. In general, a phase-locked loop (PLL) is used to generate a clock whose frequency is synchronous with the repetition frequency of received data. The clock is used to identify received data and the data is reproduced.
For example, when a non-return-to-zero (NRZ) signal to be transmitted at a bit rate of several tens of gigabits per second is adopted as a signal carrying data, the bit time is as short as several tens of picoseconds. If the signal is affected with the foregoing distortion or noise, the time during which data can be identified is very short. The phase of a clock produced by the PLL must lock onto the phase of received data with an optimal relationship maintained between the phases.
FIG. 1 shows a Hogge-type phase comparator generally employed in a PLL. FIG. 2 is a timing chart showing the waveforms of signals observed when an NRZ signal having a duty cycle of 100% is adopted as a data-carrying signal. In FIG. 2, signals (a) to (h) are signals developed at nodes (a) to (h) in FIG. 1. The duty cycle is the ratio (t/T) 100 (%) of a pulse duration t during which data or a bit “1” persists to an interval T between pulses or bits, wherein a bit rate is expressed as f=1/T.
The Hogge-type phase comparator comprises two D flip-flops 1 and 2, two exclusive OR circuits 3 and 4, and two analog rectification circuits (filters) 5 and 6. The D flip-flop 1 and exclusive OR circuit 3 detect (produce a signal e) a period φ from the change in input data (the leading or trailing edge of input data) to the leading edge of a clock. On the other hand, the D flip-flop 2 and exclusive OR circuit 4 detect (produce a signal f) a period π from the change in the output of the D flip-flop 1 (the leading or trailing edge) to the trailing edge of the clock.
The period φ provided by the exclusive OR circuit 3 varies depending on the temporal relationship between the change in the input data and the leading edge of the clock. The period π provided by the exclusive OR circuit 4 is always half the cycle of the clock. Moreover, the number of outputs φ of the exclusive OR circuit 3 is always equal to the number of outputs π of the exclusive OR circuit 4. Consequently, when the leading edge of the clock is in the center of input data, the period φ provided by the exclusive OR circuit 3 and the period π provided by the exclusive OR circuit 4 are equal to each other and are half the cycle of the clock.
Assume that the output φ of the exclusive OR circuit 3 and the output π of the exclusive OR circuit 4 are rectified by the respective filters 5 and 6 in order to produce rectified signals g and h respectively. When the rectified signal h of the output π of the exclusive OR circuit 4 is used as a reference, the rectified signal g of the output φ of the exclusive OR circuit 3 is regarded as a sawtooth wave whose level varies by the half cycle of the clock in both directions with the reference level as a center (see FIG. 2).
A time point at which the rectified outputs cross, that is, a time point at which the leading edge of the clock comes in the center of input data is regarded as an optimal time point of identification. The output frequency of a voltage-controlled oscillator (VCO) included in the PLL is controlled so that the rectified outputs will be equal to each other (g=h), whereby the leading edge of the clock stably coincides with at the optimal time point of identification within the cycle of input data.
FIG. 3 is a timing chart showing the waveforms of signals observed when an NRZ signal having a duty cycle of 75% is adopted as a data-carrying signal. In FIG. 3, signals (a) to (h) are signals developed at the nodes (a) to (h) in FIG. 1.
When the duty cycle of data deviates from 100%, the output of the PLL may lock onto a phase different from the phase onto which the output should lock. As mentioned previously, when the duty cycle of data is 100%, the data wave has only one slope in one direction within one cycle (0 to 2π) and an average signal level attained during the time equivalent to one slope is detected at the same phase over all the cycles. However, when the duty cycle deviates from 100%, the wave has two slopes in the same direction within one cycle and the average signal levels attained during the times equivalent to the two slopes are the same as each other and detected in two phases of a normal phase and an erroneous phase.
When the duty cycle of data is 75%, as long as a phase difference of the data from a clock is limited, the average signal level varies in the same manner as it does when the duty cycle if 100%. However, if the phase difference of the data from the clock exceeds 1.5π (75%), the edge of the clock comes after the trailing edge of the data. Therefore, a clock pulse produced when the phase difference is equal to or smaller than 1.5π may not be produced.
In this case, a sawtooth wave exhibits two phases within one cycle (2π) (g and h), that is, exhibits a normal phase and an erroneous phase in which the wave assumes the same average signal level as it does in the normal phase. Consequently, conventionally, if the erroneous phase locks onto the phase of a clock, the time during which data is identified becomes very short or it becomes impossible to reproduce data.
Referring to FIG. 3, a description has been made of a case where the duty cycle of data decreases from 100%. Even when the duty cycle becomes equal to or larger than 100% or, for example, 125%, a sawtooth wave exhibits two phases within one cycle thereof (2π) and has two slopes in the same direction.
Patent Documents relevant to the foregoing related art include Japanese Unexamined Patent Application Publication No. 2000-183731 (see FIG. 35 to FIG. 38) and Japanese Patent No. 3094971 (see FIG. 1 to FIG. 3).